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    • 专利摘要:
    A voltage selection circuit includes: first (101) and second (103) application nodes of first (VDD1) and second (VDD2) input voltages; a third output voltage supply node (VCORE) (102); first (SW1) and second (SW2) MOS transistors respectively connecting the first (101) and third (102) nodes and the second (103) and third (102) nodes; and a control circuit (301) adapted to hold the first (SW1) and second (SW2) transistors respectively closed and open or respectively open and closed, the control circuit (301) having a feedback loop of the third node (102). ) to the gate of the first transistor (SW1), and being adapted, during a transition phase, to control the first transistor (SW1) in linear mode to apply a DC voltage ramp to the third node (102).
    公开号:FR3053857A1
    申请号:FR1656566
    申请日:2016-07-07
    公开日:2018-01-12
    发明作者:Anthony Quelen
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    Field
    The present application relates to the field of electronic circuits in general, and relates more particularly to a circuit for selecting a supply voltage, for example for an integrated circuit.
    Presentation of the prior art
    In certain electronic devices, it is desired to be able to modify the level of the supply voltage of an integrated circuit, for example to optimize the management of electrical energy in the device. Preferably, this modification of the level of the supply voltage must be able to be carried out dynamically, that is to say without interrupting the operation of the integrated circuit.
    FIG. 1 is a simplified electrical diagram of an example of a circuit for selecting a supply voltage. The circuit of Figure 1 includes two power MOS transistors SW1 and SW2. The transistor SW1 connects, via its conduction nodes (source and drain), a node 101 for applying a first input supply voltage VDD1 to a node 102 for supplying an output supply voltage VCORE . The transistor SW2 connects, via its conduction nodes, a node 103
    B15068 - DD16944ST of application of a second input supply voltage VDD2 lower than the voltage VDD1 at the node VCORE. The voltage selection circuit of FIG. 1 further comprises a control circuit 104 connected to the gates of the transistors SW1 and SW2, configurable for, in a first configuration, keeping the transistors SW1 and SW2 respectively closed (passing) and open (blocked) ), and, in a second configuration, maintain the transistors SW1 and SW2 respectively open and closed. In the first configuration, the voltage VCORE on the node 102 is substantially equal to the voltage VDD1, and, in the second configuration, the voltage VCORE on the node 102 is substantially equal to the voltage VDD2. The node 102 is intended to be connected to a load supply node (not shown), for example an integrated circuit. Thus, the circuit of FIG. 1 makes it possible, via its control circuit 104, to select one or the other of the voltages VDD1 and VDD2 for supplying the load circuit.
    A problem which arises in such a voltage selection circuit is that of controlling the transitions between the first and second configurations. In particular, to limit energy losses, the transistors SW1 and SW2 are generally chosen to have low series resistances in the on state. Thus, if the two transistors SW1 and SW2 are closed simultaneously, even for a short time, a strong current flows between the nodes 101 and 103, which can lead to degradations. In addition, if the two transistors SW1 and SW2 are simultaneously open, even for a short time, a voltage drop can occur on node 102, which can lead to malfunctions of the load circuit.
    FIG. 2 is a simplified electrical diagram illustrating an example of architecture of the supply voltage selection circuit which has been proposed in an attempt to solve this problem.
    B15068 - DD16944ST
    In this example, it is considered that the input supply voltage VDD1 applied to the node 101 is greater than the input supply voltage VDD2 applied to the node 103. In the circuit of FIG. 2, the transistor SW1 of FIG. 1 is replaced by a plurality of elementary transistors SWly of smaller dimensions (and therefore having a higher series resistance in the on state) connected in parallel between the nodes 101 and 102 (with i integer going from 1 to n and n integer greater than 1). The gates of the elementary transistors SWly and of the transistor SW2 are connected to a digital control circuit 201. The elementary transistors SWly are individually controllable in the open or closed state by the control circuit 201. The control circuit 201 is configurable for, in a first configuration, keeping all of the SWly transistors closed and the transistor SW2 open so as to apply the voltage VDD1 on node 102, and, in a second configuration, keeping all of the SWly transistors open and the transistor SW2 closed so as to apply the voltage VDD2 to the node 102. The control circuit 201 is also connected to the node VCORE and includes a digital feedback loop making it possible, during transition phases between the first and second configurations, to close / open one by one the SWly transistors to control the speed of increase / decrease of the VCORE voltage on node 102.
    Examples of architectures of this type are described in particular in the publications entitled A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling (Sylvain Miermont, PATMOS 2007, LNCS 4644, pp. 556-565), Advanced Control Design for Voltage Scaling Converters (Carolina Albea, Industrial Electronics, 2008. IECON 2008. 34th Annual Conference of IEEE), High Performance Control Design for Dynamic Voltage Scaling Devices (Carolina Albea, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS, VOL. 58, NO. 12, DECEMBER 2011), and Robust Saturated Control for Low-Power Circuits (Carolina
    B15068 - DD16944ST
    Albea, IEEE TRANSACTIONS ON CONTROL SYSTEMS TECHNOLOGY, VOL. 21, NO. 2, MARCH 2013).
    A drawback of this type of architecture resides in the need to supply the control circuit with a clock signal (not shown) of relatively high frequency (typically several hundred MHz), which leads to high electrical consumption during the phases of transition between the first and second configurations. In addition, during the transition phases between the first and second configurations, there may be an undulation of the voltage VCORE on the node 102, induced by the digital regulation loop. In addition, this type of architecture does not completely prevent drops in the VCORE voltage on node 102, nor the circulation of high currents between nodes 101 and 103, during the transition phases between the first and second configurations. . Furthermore, this type of architecture can be subject to malfunctions if the load current drawn on the node 102 by the load circuit is too high or fluctuates during the transition phases between the first and second configurations.
    It would be desirable to be able to have a circuit for selecting a supply voltage, this circuit overcoming all or part of the drawbacks of existing circuits.
    summary
    Thus, one embodiment provides a circuit for selecting a supply voltage, comprising: first and second nodes adapted to receive first and second input supply voltages respectively; a third node adapted to supply an output supply voltage; a first power MOS transistor connecting the first node to the third node; a second power MOS transistor connecting the second node to the third node; and a control circuit adapted, in a first configuration, to maintain the first and second transistors respectively closed and open, and, in a second configuration, to maintain the first and second transistors respectively open and closed, the control circuit
    B15068 - DD16944ST comprising a feedback loop from the third node to the gate of the first transistor, and being adapted, during a transition phase from the first to the second configuration or from the second to the first configuration, to control the first transistor in linear mode to apply a continuous voltage ramp on the third node.
    According to one embodiment, the control circuit comprises: a voltage ramp generator; and a first linear regulation circuit of which a first input node is connected to the third node, of which a second input node is connected to an output node of the ramp generator, and of which an output node is connected to the gate of the first transistor.
    According to one embodiment, the first linear regulation circuit is adapted to adjust a control signal applied, via its output node, to the gate of the first transistor, so as to slave the output voltage to a reference voltage applied to its second input node.
    According to one embodiment, the selection circuit further comprises a second linear regulation circuit, a first input node of which is connected to the third node, a second input node of which is connected to an output node of the ramp generator. , and of which an output node is connected to the gate of the second transistor.
    According to one embodiment, the selection circuit further comprises a circuit for detecting an inversion of the current flowing in the second transistor.
    According to one embodiment, the detection circuit comprises a measurement transistor arranged to be crossed by a measurement current proportional to the current passing through the second transistor, and a current comparator adapted to compare said measurement current with a threshold.
    According to one embodiment, the selection circuit further comprises a circuit for comparing the output voltage with a threshold.
    B15068 - DD16944ST
    According to one embodiment, the selection circuit further comprises a circuit for generating a predetermined delay.
    According to one embodiment, the first power MOS transistor is connected to the first node by means of a first additional MOS transistor having leakage currents in the blocked state lower than that of the first power MOS transistor, and in which the second power MOS transistor is connected to the second node by means of a second additional MOS transistor having leakage currents in the blocked state lower than that of the second power MOS transistor.
    According to one embodiment, the control circuit is adapted, in a third configuration, to maintain the first and second power MOS transistors and the first and second additional MOS transistors in the open state.
    According to one embodiment, the first input supply voltage is greater than the second input supply voltage, the control circuit being adapted, during a downward transition phase between the first and second configurations, to: control the first transistor in linear mode to apply a decreasing DC voltage ramp to the third node; detecting a passage of the output voltage to a level substantially equal to that of the second input supply voltage; and when the output voltage reaches a level substantially equal to that of the second input supply voltage, closing the second power MOS transistor and opening the first power MOS transistor.
    According to one embodiment, the first input supply voltage is greater than the second input supply voltage, the control circuit being adapted, during an upward transition phase between the first and second configurations, to: command, the first transistor in linear mode to apply a ramp of increasing DC voltage
    B15068 - DD16944ST on the third node; detecting an inversion of the current flowing in the second transistor; when the current flowing in the second transistor reverses, opening the second transistor; and after a predetermined delay, turn off the first power MOS transistor.
    Brief description of the drawings
    These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments made without implied limitation in relation to the attached figures among which:
    FIG. 1, previously described, is a simplified electrical diagram of an example of a circuit for selecting a supply voltage;
    FIG. 2, previously described, is a simplified electrical diagram of another example of a circuit for selecting a supply voltage;
    FIG. 3 is an electrical diagram of an example of a circuit for selecting a supply voltage according to an embodiment;
    Figures 4 and 5 are timing diagrams illustrating an example of an operating mode of the circuit of Figure 3;
    Figure 6 is an electrical diagram of an exemplary embodiment of a linear voltage regulation circuit of the circuit of Figure 3; and FIG. 7 is an electric diagram of another exemplary embodiment of a linear voltage regulation circuit of the circuit of FIG. 3.
    detailed description
    The same elements have been designated by the same references to the different figures and, moreover, the various figures are not drawn to scale. For the sake of clarity, only the elements which are useful for understanding the embodiments described have been shown and are detailed. In particular, the various uses that can be made of the supply voltage selection circuits described have no
    B15068 - DD16944ST not been detailed, the embodiments described being compatible with the usual applications of supply voltage selection circuits. Unless specified otherwise, the expressions approximately, appreciably, and of the order of mean to the nearest 10%, preferably to the nearest 5%. Furthermore, the term connected is used to designate a direct electrical connection, without an intermediate electronic component, for example by means of one or more conductive tracks or conductive wires, and the term coupled or the term connected, to designate an electrical connection which can be direct (meaning then connected) or indirect (i.e. via one or more intermediate components).
    According to one aspect of an embodiment, a supply voltage selection circuit of the type described in relation to FIG. 1 is provided, but in which the transistors SW1 and / or SW2 are controlled in linear mode during the phases of transition between the first and second configurations, so as to control the variation of the voltage VCORE on the node 102.
    FIG. 3 is an electrical diagram of an example of a circuit for selecting a supply voltage according to an embodiment.
    The circuit of FIG. 3 comprises two MOS transistors of power SW1 and SW2. The transistor SW1 connects, via its conduction nodes (source and drain), a node or a terminal 101 for applying a first continuous input supply voltage VDD1 to a node or a terminal 102 for supplying a continuous output supply voltage VCORE, and the transistor SW2 connects, via its conduction nodes, a node or a terminal 103 for applying a second continuous input supply voltage VDD2 to the node 102 for supplying the VCORE voltage. In the example of FIG. 3, the conduction node of transistor SW1, respectively SW2, opposite to node 102 is not connected directly to node 101, respectively 103, but is connected to node 101, respectively 103 via d 'a MOS transistor SWPG1, respectively SWPG2. In the example shown, the
    B15068 - DD16944ST transistors SW1 and SW2 are P-channel MOS transistors, and transistors SWPG1 and SWPG2 are N-channel MOS transistors. The transistors SW1 and SW2 have their drains connected to node 102, and their sources connected respectively to the source. of the transistor SWPG1 and at the source of the transistor SWPG2. The transistors SWPG1 and SWPG2 have their drains connected respectively to node 101 and to node 102.
    The voltage selection circuit of FIG. 3 further comprises a control circuit 301 connected to the gates of the transistors SW1 and SW2, configurable for, in a first configuration, keeping the transistors SW1 and SW2 respectively closed and open, and, in a second configuration, maintain the transistors SW1 and SW2 respectively open and closed. In the first configuration, the voltage VCORE on the node 102 is substantially equal to the voltage VDD1, and, in the second configuration, the voltage VCORE on the node 102 is substantially equal to the voltage VDD2. It will be noted that, in operation, the transistors SWPG1, respectively SWPG2, are kept closed when the transistors SW1, respectively SW2, are controlled in the on state. As will be explained in more detail in relation to FIGS. 4 and 5, the transistors SWPG1, SWPG2 only serve to limit the leakage through the transistors SW1, SW2 when the latter are in the blocked state. By way of example, when the selection circuit is not used, that is to say when none of the input supply voltages VDD1, VDD2 is selected to supply the node 102, the transistors SW1, SW2 are set to the open state, and the transistors SWPG1 and SWPG can be kept in the open state so as to limit leakage to ground through in particular the transistors SW1 and SW2.
    The control circuit 301 includes an analog feedback loop from node 102 to the gate of transistor SW1, and an analog feedback loop from node 102 to the gate of transistor SW2. The circuit 301 is adapted, during the transition phases from the first to the second configuration
    B15068 - DD16944ST or from the second to the first configuration, to control the transistor SW1 or the transistor SW2 in linear mode to apply a predetermined voltage ramp on the node 102, and thus control the evolution of the voltage VCORE.
    In the example of FIG. 3, the voltage selection circuit is provided to be able to operate indifferently whether the input supply voltage VDD1 applied to the node 101 is greater or less than the input supply voltage VDD2 applied to node 103. This allows greater flexibility of use, especially when mounting the circuit in an electronic device. As will be explained in more detail below, the circuit can however be simplified when it is known in advance which of the input supply voltages VDD1 and VDD2 is the highest.
    The voltage selection circuit of FIG. 3 comprises a node or a terminal 303 intended, in operation, to receive a supply voltage VMAX substantially equal to the higher of the two input supply voltages VDD1 and VDD2. In the example shown, the node 303 is connected to a node 305 for supplying an internal supply voltage VMAX_INT via a MOS transistor SWPGVMAX. In the example shown, the transistor SWPGVMAX is an N-channel MOS transistor whose drain is connected to node 303 and whose source is connected to node 305. The voltage selection circuit of FIG. 3 further comprises a node or a terminal 304 intended to receive a reference potential VSS, for example the ground, to which all the voltages of the circuit are referenced.
    In the example of FIG. 3, the transistors SWPG1, SWPG2, SWPGVMAX have the function of limiting the leakage currents in the voltage selection circuit. In particular, the transistors SWPG1, SWPG2 are chosen to present leaks in the blocked state lower than those of the transistors SW1, SW2. The transistors SWPG1, SWPG2, SWPGVMAX are for example identical to the manufacturing dispersions. These transistors are for example more resistive than the transistors SW1, SW2. He can then
    B15068 - DD16944ST be advantageous, to drive the transistors SWPG1, SWPG2, SWPGVMAX, to apply control voltages EN_SWPG1, EN_SWPG2, ENJ3WPGVMAX on their gates higher than the supply voltage VMAX of the circuit. For this, in the example of FIG. 3, the voltage selection circuit further comprises a node or a terminal 312 for applying a DC supply voltage VANA greater than the voltage VMAX. For example, the transistors SW1, SW2 are faster than the transistors SWPG1, SWPG2, SWPGVMAX. The transistors SW1, SW2 for example have a thinner gate oxide than the transistors SWPG1, SWPG2, SWPGVMAX. By way of example, the transistor SWPGVMAX can be controlled in the open state when the selection circuit is not used, that is to say when none of the input supply voltages VDD1, VDD2 n 'is selected to supply the node 102, so as to limit leaks to ground.
    The control circuit 301 comprises a linear regulation circuit LDO1 of which an input node el is connected to the node 102 and of which an output node s is connected to the gate of the transistor SW1. The circuit LDO1 forms an analog feedback loop adapted to control the transistor SW1 in linear mode to control the voltage VCORE supplied to the node 102. In the example shown, the regulation circuit LDO1 comprises an input node e5 intended to receive a setpoint voltage VCTRL to be transferred to the node 102. The circuit LDO1 is adapted to adjust the control signal applied, via its node s, to the gate of the transistor SW1, so as to control the voltage VCORE on the setpoint voltage VCTRL . In this example, the LDO1 regulation circuit further comprises an input node e4 intended to receive an EN_LDO1 activation signal for regulating the LDO1 circuit, an input node e3 intended to receive a command SWON1 signal to the closed state (passing) of transistor SW1, and an input node e2 intended to receive a control signal SWOFF1 in the open state (blocked) of transistor SW1. The regulation circuit
    B15068 - DD16944ST
    LDO1 further comprises a supply node p connected to the node 305 for supplying the internal supply voltage VMAX_INT.
    The control circuit 301 further comprises a linear regulation circuit LDO2 of which an input node el is connected to the node 102 and of which an output node s is connected to the gate of the transistor SW2. The LDO2 circuit forms a feedback loop adapted to control the transistor SW2 in linear mode to control the voltage VCORE supplied on the node 102. In the example shown, the regulation circuit LDO2 comprises an input node e5 intended to receive a setpoint voltage VCTRL to be transferred to node 102. The circuit LDO2 is adapted to adjust the control signal applied, via its node s, to the gate of transistor SW2, so as to control the voltage VCORE on the setpoint voltage VCTRL. In this example, the LDO2 regulation circuit further comprises an input node e4 intended to receive an activation signal EN_LDO2 for regulating the LDO2 circuit, an input node e3 intended to receive a control signal SWON2 at the closed state (on) of transistor SW2, and an input node e2 intended to receive a control signal SWOFF2 in the open state (blocked) of transistor SW2. The LDO2 regulation circuit further comprises a supply node p connected to the node 305 for supplying the internal supply voltage VMAX_INT. The LDO2 regulation circuit is for example identical or similar to the LDO1 regulation circuit. Examples of embodiments of the linear regulation circuits LDO1, LDO2 will be detailed below in relation to FIGS. 6 and 7.
    The control circuit 301 further comprises an RMP circuit for generating voltage ramps. The RMP circuit comprises an output node s connected to the input nodes e5 of the linear regulation circuits LDO1 and LDO2 and supplying the setpoint voltage VCTRL applied to the circuits LDO1 and LDO2. In the example shown, the RMP circuit comprises an input node el intended to receive a control signal CTRLUP and an input node e2 intended to receive a control signal CTRLDW. The RMP circuit is adapted, when the control signal CTRLUP is activated, to
    B15068 - DD16944ST generate on its node s a predetermined increasing voltage ramp going from the lowest of the voltages VDD1 and VDD2 to the highest of the voltages VDD1 and VDD2, and, when the control signal CTRLDW is activated, to generate on its node s a predetermined decreasing voltage ramp going from the highest of the voltages VDD1 and VDD2 to the lowest of the voltages VDD1 and VDD2. The RMP circuit further comprises a supply node p connected to the node 305 for supplying the internal supply voltage VMAX_INT. The production of the RMP voltage ramp generation circuit has not been detailed, the embodiments described being compatible with all or most of the known voltage ramp generation circuits.
    The control circuit 301 also includes an LED circuit for generating a predetermined delay. The LED circuit includes an input node el intended to receive a signal TRLOORHI, and an output node s. The LED circuit is adapted to supply, on its output node s, a signal TRLOORHI_DEL delayed image of the input signal TRLOORHI. More particularly, the LED circuit is adapted to reproduce on its output s, with a predetermined delay, a change of state of the signal TRLOORHI applied to its input node el. The LED circuit further comprises a supply node p connected to the node 305 for supplying the internal supply voltage VMAX_INT. The construction of the DEL delay generation circuit has not been detailed, the embodiments described being compatible with all or most of the known delay generation circuits.
    The control circuit 301 of FIG. 3 further comprises a MOS transistor SW1_REP whose gate is connected to the gate of the transistor SW1 and whose conduction nodes are respectively connected to the common conduction node between the transistors SW1 and SWPG1 and to a node 306 and a MOS transistor SW2_REP whose gate is connected to the gate of transistor SW2 and whose conduction nodes are connected respectively to the common conduction node between transistors SW2 and SWPG2 and to a node 308. In operation, node 306 provides a
    B15068 - DD16944ST current IREP1 substantially proportional to the current flowing in the transistor SW1, and the node 308 supplies a current IREP2 substantially proportional to the current flowing in the transistor SW2. The transistors SW1_REP, respectively SW2_REP are for example reduced images of the transistors SW1, respectively SW2, that is to say that they have substantially the same characteristics as the transistors SW1, respectively SW2, except for their width of channel, lower than that of the transistors SW1, respectively SW2, and therefore of their source-drain resistance in the on state, higher than that of the transistors SW1, respectively SW2. The transistors SW1_REP and SW2_REP are chosen so that the coefficients of proportionality between the current IREP1 and the current flowing in the transistor SW1 on the one hand, and between the current IREP2 and the current flowing in the transistor SW2 on the other hand, are substantially equal. The transistors SW1_REP and SW2_REP are for example substantially identical. In the example shown, the transistors SW1_REP, respectively SW2_REP are P-channel MOS transistors whose sources are connected to the sources of the transistors SW1, respectively SW2, and whose drains are connected to the nodes 306, respectively 308.
    The control circuit 301 of FIG. 3 further comprises an ICMP current comparator, a first input node e- of which is connected on the one hand to the node 306 for supplying the current IREP1 by a first switch Kl, and on the other leaves at node 308 for supplying current IREP2 by a second switch K2, and a second input node e + of which is intended to receive a reference current IREVLIM. The ICMP current comparator comprises an output node s and is adapted to supply, on this node s, a voltage VIREVLIMB changing level when the current applied to its input node e- reaches a level substantially equal to that of the applied current on its input node e +. The ICMP current comparator further comprises a supply node p connected to the node 305 for supplying the internal supply voltage VMAX INT. The realization of the circuit
    B15068 - DD16944ST ICMP current comparison has not been detailed, the embodiments described being compatible with all or most of the known current comparison circuits.
    The control circuit 301 of FIG. 3 further comprises a voltage comparator VCMP of which a first input node e- is connected on the one hand to the node 101 for applying the input supply voltage VDD1 by l 'via a switch K3, and on the other hand to the node 103 of application of the input supply voltage VDD2 via a switch K4, and of which a second input node e + is connected at node 102 for supplying the voltage VCORE. The voltage comparator VCMP comprises an output node s and is adapted to supply, on this node s, a voltage VCOVVDD changing level when the voltage applied to its input node e + reaches a level substantially equal to that of the applied voltage on its input node e-. The voltage comparator VCMP further comprises a supply node p connected to the node 305 for supplying the internal supply voltage VMAX_INT. The construction of the VCMP voltage comparison circuit has not been detailed, the embodiments described being compatible with all or most of the known voltage comparison circuits.
    In this example, the control circuit 301 further comprises an asynchronous sequencing circuit (without clock) FSM, implementing for example a finite state machine. The circuit
    FSM sequencing includes: if bound at node input e2 of a node of exit generator ramp RMP and adapted to provide the control signal CTRLDW; a node of exit s2 bound at node input el of generator ramp RMP and adapted to provide the control signal CTRLUP; a node of exit s3 bound at node input e3 of
    linear regulation circuit LDO1 and adapted to supply the control signal SWON1;
    B15068 - DD16944ST an output node s4 connected to the input node e2 of the linear regulation circuit LDO1 and adapted to supply the control signal SWOFF1;
    an output node s5 connected to the input node e3 of the linear regulation circuit LDO2 and adapted to supply the control signal SWON2;
    an output node s6 connected to the input node e2 of the linear regulation circuit LDO2 and adapted to supply the control signal SWOFF2;
    an output node s 7 connected to the input node e4 of the linear regulation circuit LDO2 and adapted to supply the control signal EN_LDO2;
    an output node s8 connected to the input node e4 of the linear regulation circuit LDO1 and adapted to supply the control signal EN_LDO1;
    an output node s9 connected to the input node el of the delay circuit DEL and adapted to supply the control signal TRLOORHI;
    an output node slO connected to the gate of the transistor SWPG1 and adapted to supply a control voltage EN_SWPG1 in the open or closed state of the transistor SWPG1;
    an output node sll connected to the gate of the transistor SWPG2 and adapted to supply a control voltage EN_SWPG2 in the open or closed state of the transistor SWPG2;
    an output node sl2 connected to the gate of the transistor SWPGVMAX and adapted to supply a control voltage EN_SWPGVMAX in the open or closed state of the transistor SWPGVMAX;
    an entry node el bound at output node s of VCMP voltage comparator and adapted at receive voltage of VCOWDD output of the VCMP comparator; an e2 input node bound at output node s of
    LED delay circuit and adapted to receive the output voltage TRLOORHI_DEL of the LED circuit; and
    B15068 - DD16944ST an input node e3 connected to the output node s of the ICMP current comparator and adapted to receive the output voltage VIREVLIMB of the ICMP comparator.
    In the example shown, the sequencing circuit FSM further comprises a control input 310 on one or more bits (DIGBUS [1: x]) making it possible to control the voltage selection circuit in the first configuration (transistor SW1 and SW2 closed and open respectively) or in the second configuration (transistor SW1 and SW2 respectively open and closed), and, if necessary, to configure certain parameters of circuit 301. The segregation circuit FSM further comprises a supply node pl connected at node 303 for supplying the voltage VMAX. In this example, the segregation circuit FSM further comprises a supply node p2 connected to the node 312 for applying the VANA voltage. The creation of the FSM segregation circuit has not been detailed, the production of such a circuit being within the reach of those skilled in the art from the functional indications described in the present application.
    FIGS. 4 and 5 are timing diagrams illustrating schematically an example of an operating mode of the supply voltage selection circuit of FIG. 3.
    In this example, it is considered that the input supply voltage VDD1 is greater than the input supply voltage VDD2. In this configuration, during the transition phases of the selection circuit, the switches Kl and K2 are kept respectively open (blocked) and closed (passing), so as to connect the input node e + of the current comparator ICMP to node 308 for supplying the current IREP2, and the switches K3 and K4 are kept respectively open and closed, so as to connect the input node e- of the voltage comparator VCMP to the node 103 of application of the voltage VDD2.
    FIG. 4 illustrates the operation of the circuit during a downward transition phase, that is to say during a transition phase of the first configuration (transistors SW1
    B15068 - DD16944ST and SW2 respectively closed and open) in the second configuration (transistors SW1 and SW2 respectively open and closed). Figure 4 represents more particularly the evolution, as a function of time, of the signals EN_SWPG2, EN_SWPG1, EN_SWPGVMAX, EN_LDO1, CTRL_DW, SWON2, SWON1, SWOFF1, SWOFF2, VCOWDD, TRLOORHI, TRLOORHI_DEL and VCORE falling transition. FIG. 4 also represents the evolution, as a function of time, of a signal TR_START for controlling a transition of the selection circuit between the first and second configurations. In this example, we consider that the signals TR_START, EN_SWPG2, EN_SWPG1, EN_SWPGVMAX, EN_LDO1, CTRLDW, SWON2, SWON1, SWOFF1, SWOFF2, VCOWDD, TRLOORHI, TRLOORHI_DEL are binary signals which can each take a high state, either (i.e. lower than the high state).
    Before the start of the downward transition phase, the selection circuit is in the first configuration (transistors SW1 and SW2 respectively closed and open). In this configuration, the signal TR_START is in the low state, the signal EN_SWPG2 is in the low state so as to keep the transistor SWPG2 open, the signal EN_SWPG1 is in the high state so as to keep the transistor SWPG1 closed, the signal EN_SWPGVMAX is in the high state so as to keep the transistor SWPGVMAW closed, the signal EN_LDO1 is in the low state so as to deactivate the linear regulation function of the circuit LDO1, the signal CTRLDW is in the low state, the signals SWON1 and SWOFF1 are respectively in the high state and in the low state so as to force the maintenance in the closed state of the transistor SW1 by the circuit LDO1, the signals SWON2 and SWOFF2 are respectively in the low state and in the high state so as to force the transistor SW2 to remain in the open state by the circuit LDO2, the signal VCOWDD of output of the comparator VCMP is in the high state, the signals TRLOORHI of input and TRLOORHI_DEL of output of DEL delay circuit is low, and VCORE voltage is substantially equal at voltage VDD1.
    At a time t0 at the start of a downward transition phase, the signal TR_START goes high. In this
    B15068 - DD16944ST instant, the signal EN_SWPG2 is set high so as to close the transistor SWPG2. In addition, the signal EN_LDO1 is set high so as to activate the linear regulation function of the circuit LDO1, and the signal SWON1 is set low so as to cease forcing the maintenance in the closed state of transistor SW1 by circuit LDO1. In addition, the signal CTRLDW is set high, so as to control the supply of a ramp of decreasing voltage by the ramp generation circuit RMP. The circuit RMP then generates on its output node s a voltage VCTRL decreasing continuously from the value VDD1 to the value VDD2 according to a predetermined ramp. This voltage VTCRL is applied to the setpoint input e5 of the linear regulation circuit LDO1. The circuit LDO1 then regulates the control signal applied to the gate of the transistor SW1 so as to reproduce the reference voltage VCTRL on the node 102. The voltage VCORE thus decreases continuously, for example linearly, from the value VDD1 to the value VDD2, substantially following the setpoint slope generated by the RMP circuit.
    At an instant tl after the instant t0, the voltage VCORE reaches the level VDD2, which causes a change of state (passage to the low state in this example) of the output voltage VCOVVDD of the voltage comparator VCMP. This change of state of the signal VCOVVDD is detected by the sequencing circuit FSM, and marks the end of the downward transition phase. The signal EN_LDO1 is then set to the low state so as to interrupt the linear regulation function implemented by the circuit LDO1, and the signal SWOFF1 is set to the high state so as to control the opening of the transistor SW1 by the LDO1 circuit. In addition, the signals SWON2 and SWOFF2 are set respectively to the high state and to the low state, so as to control the closing of the transistor SW2 by the circuit LDO2. In addition, the signal EN_SWPG1 is set low, so as to control the opening of the transistor SWPG1. The CTRLDW signal is also reset to low. As an example, the duration T ^ w = tl-tO of the downward transition, corresponding substantially to the time taken by the ramp
    B15068 - DD16944ST of VCTRL voltage to go from the VDD1 value to the VDD2 value, is fixed at a value between 10 ns and 1 ms, for example of the order of 100 ns.
    FIG. 5 illustrates the operation of the circuit during a rising transition phase, that is to say during a transition phase from the second configuration (transistors SW1 and SW2 respectively open and closed) to the first configuration ( transistors SW1 and SW2 respectively closed and open). Figure 5 represents more particularly the evolution, as a function of time, of the signals TR_START, EN_SWPG1, EN_SWPG2, EN_SWPGVMAX, EN_LDO1, CTRLUP, SWON1, SWOFF1, SWOFF2, SWON2, VIREVLIMB, TRLOORHI, TRLOORHI_DEL and VCORE of the circuit during rising transition phase. As in the example in FIG. 4, it is considered that the signals TR_START, EN_SWPG1, EN_SWPG2, EN_SWPGVMAX, EN_LDO1, CTRLUP, SWON1, SWOFF1, SWOFF2, SWON2, VIREVLIMB, TRLOORHI, TRLOORHI_DEL are each binary state signals high is a low state.
    Before the start of the rising transition phase, the selection circuit is in the second configuration (transistors SW1 and SW2 respectively open and closed). In this configuration, the signal TR_START is in the low state, the signal EN_SWPG1 is in the low state so as to keep the transistor SWPG1 open, the signal EN_SWPG2 is in the high state so as to keep the transistor SWPG2 closed, the signal EN_SWPGVMAX is in the high state so as to keep the transistor SWPGVMAW closed, the signal EN_LDO1 is in the low state so as to deactivate the linear regulation function of the circuit LDO1, the signal CTRLUP is in the low state, the signals SWON1 and SWOFF1 are respectively in the low state and in the high state so as to force the maintenance in the open state of the transistor SW1 by the circuit LDO1, the signals SWON2 and SWOFF2 are respectively in the high state and in the low state so as to force the transistor SW2 to be kept in the closed state by the LDO2 circuit, the signal VIREVLIMB of output from the ICMP comparator is in the high state, the input signals TRLOORHI and TRLOORHI_DEL
    B15068 - DD16944ST output of the DEL delay circuit are in the low state, and the voltage VCORE is substantially equal to the voltage VDD2.
    At an instant t0 at the start of an upward transition phase, the signal TR_START goes high. At this time, the signal EN_SWPG1 is set high so as to close the transistor SWPG1. In addition, the signal EN_LDO1 is set high so as to activate the linear regulation function of the circuit LDO1, and the signal SWOFF1 is set low so as to stop forcing it to remain open. of transistor SW1 by circuit LDO1. In addition, the signal CTRLUP is set high, so as to control the supply of an increasing voltage ramp by the RMP ramp generation circuit. The circuit RMP then generates on its output node s a voltage VCTRL increasing continuously from the value VDD2 to the value VDD1 according to a predetermined ramp. This voltage VTCRL is applied to the setpoint input e5 of the linear regulation circuit LDO1. The circuit LDO1 then regulates the control signal applied to the gate of the transistor SW1 so as to reproduce the reference voltage VCTRL on the node 102. The voltage VCORE thus increases continuously, for example linearly, from the value VDD2 to the value VDD1, substantially following the setpoint slope generated by the RMP circuit. At time t0, the state of the signal TRLOORHI is further modified (set high in this example), so as to trigger the generation of a delay by the LED circuit.
    At an instant tl after the instant t0, the voltage VCORE reaches a level such that the current flowing in the transistor SW2 tends to reverse. This inversion is detected by the current comparison circuit ICMP, which compares a current IREP2 proportional to the current flowing in the transistor SW2 to a reference current IREVLIM, for example zero or close to zero, for example between 0 and 10 mA. The instant tl corresponds in this example to the instant of change of state of the output voltage VIREVLIMB of the current comparator ICMP, when the current IREP2 reaches the level IREVLIM. This change
    B15068 - Status DD16944ST is detected by the FSM sequencing circuit. The signals SWON2 and SWOFF2 are then set respectively to the low state and to the high state so as to control the opening of the transistor SW2 by the circuit LDO2. In addition, the signal EN_SWPG2 is set low so as to open the transistor SWPG2.
    At an instant t2 posterior to the instant tl, the delay generated by the delay circuit DEL expires, that is to say that the signal TRLOORHI_DEL changes state (goes high in this example). The duration t2-t0 is a predetermined duration fixed by the delay circuit DEL. This duration is chosen at least equal to the time taken by the voltage ramp VCTRL generated by the circuit RMP to go from the value VDD2 to the value VDD1. Thus, at time t2, the voltage VCORE is substantially equal to the voltage VDD1. The instant t2 marks the end of the rising transition phase. The change of state of the signal TRLOORHI_DEL is detected by the sequencing circuit FSM. The signal EN_LDO1 is then set to the low state to interrupt the linear regulation function implemented by the circuit LDO1, and the signal SWON1 is set to the high state so as to control the closing of the transistor SW1 by the circuit LDO1 . The signals CTRLUP, TRLOORHI and TRLOORHI_DEL can also be reset to the low state pending a new downward transition. By way of example, the duration T U p = t2-t0 of the rising transition, fixed by the delay circuit DEL and corresponding substantially to the time taken by the voltage ramp VCTRL to go from the value VDD2 to the value VDD1, is set to a value between 10 ns and 1 ms, for example of the order of 100 ns.
    An advantage of the circuit of FIG. 3 is that it makes it possible to control the variations of the voltage VCORE during the transition phases between the first and second configurations of the voltage selection circuit.
    In addition, the circuit of FIG. 3 makes it possible to control the reverse current capable of flowing in the transistor SW2 during the downward transition phases.
    B15068 - DD16944ST
    In addition, in the circuit of FIG. 3, the control of the transitions between the first and second configurations is carried out asynchronously, and does not require a clock signal.
    In addition, the circuit of Figure 3 has a relatively low power consumption and size.
    The architecture of FIG. 3 can easily be repeated, for example in several regions of an integrated circuit chip, so as to produce a distributed power supply switchable between the two levels VDD1 and VDD2.
    In addition, the architecture of FIG. 3 can easily be adapted to increase the number of input supply voltages, that is to say to produce a circuit making it possible to select a supply voltage VCORE from a number VDDi input supply voltages greater than 2.
    Another advantage of the circuit of FIG. 3 is that its behavior during the transition phases between the first and second configurations is independent of the load current drawn by the load circuit on the node 102.
    In addition, the circuit of FIG. 3 does not generate undulations of the voltage VCORE on the node 102 during the transition phases.
    FIG. 6 is an electrical diagram of an exemplary embodiment of the linear voltage regulation circuit LDO1 of the circuit of FIG. 3. In FIG. 6, we have represented, in addition to the circuit LDO1, the power transistor SW1, as well as nodes 101 (VDDI), 102 (VCORE) and 304 (VSS) of the voltage selection circuit.
    The LDO1 circuit of FIG. 6 includes a bias circuit (BIAS), a high power node p + is connected to the power node p of the LDO1 circuit and a low power node p- of which is connected to the node 304 ( VSS) corresponding to the mass of the circuit. The BIAS bias circuit comprises a node if supplying a BIASP bias voltage, a node s2 providing a supply voltage
    B15068 - DD16944ST VB polarization, and a node s3 for supplying a BIASN polarization voltage. The LDO1 circuit further comprises a MOS transistor 601 connecting, via its conduction nodes, the supply node p of the LDO1 circuit to the output node si of the BIAS bias circuit, and a MOS transistor 603 connecting, via its conduction nodes , the output node s3 of the BIAS bias circuit at node 304. In this example, transistor 601 is a P-channel MOS transistor whose source is connected to node p and whose drain is connected to node if, and the transistor 603 is an N-channel MOS transistor whose source is connected to node 304 and whose drain is connected to node s3. The gate of transistor 601 is connected to node e4 of application of the activation control signal EN_LDO1 of circuit LDO1, and the gate of transistor 603 is connected to the same node e4 but via an inverter 605, so that transistors 601 and 603 are controlled simultaneously in the open state or simultaneously in the closed state depending on the state of the signal EN_LDO1. The circuit LDO1 of FIG. 6 further comprises a MOS MPBIAS transistor connecting, via its conduction nodes, the supply node p of the circuit LDO1 to its output node s, that is to say to the gate of the transistor SW1. In this example, the MPBIAS transistor is a P-channel MOS transistor whose source is connected to node p and whose drain is connected to node s. The gate of the MPBIAS transistor is connected to the output node if of the BIAS circuit. The LDO1 circuit further comprises a MOS transistor MNVB connecting, via its conduction nodes, the output node s of the LDO1 circuit to an intermediate node ni, and a MOS transistor MNBIAS connecting, via its conduction nodes, the node or to the node 304. In this example, the MNVB and MNBIAS transistors are N-channel MOS transistors. The drain and the source of the MNVB transistor are connected respectively to the node s and to the node ni, and the drain and the source of the transistor MNBIAS are connected respectively. at the node ni and at the node 304. The gate of the transistor MNVB is connected to the output node s2 of the circuit BIAS, and the gate of the transistor MNBIAS is connected to the
    B15068 - DD16944ST output node s3 of the BIAS circuit. The circuit LDO1 of FIG. 6 further comprises a MOS transistor MPREG connecting, via its conduction nodes, the input node el of the circuit LDO1, that is to say the node 102 for supplying the voltage VCORE, to the internal node ni. In this example, the transistor MPREG is a P-channel MOS transistor whose source is connected to the node el and whose drain is connected to the node ni. The gate of the transistor MPREG is connected to the node e5 for applying the reference voltage VCTRL. In this example, the circuit LDO1 further comprises a MOS transistor MPDIS connected in series, via its conduction nodes, with a resistance RDISLIM, between the input node el of the circuit LDO1 and the node 304. In this example, the transistor MPDIS is a P-channel MOS transistor whose source is connected to node el and whose drain is connected to a first end of the RDISLIM resistor, the second end of the RDISLIM resistor being connected to node 304. The gate of the MPDIS transistor is connected to node e5 for applying the setpoint voltage VCTRL. The circuit LDO1 of FIG. 6 further comprises a MOS transistor MPOFF connecting, via its conduction nodes, the supply node p of the circuit LDO1 to its output node s, and a MOS transistor MPON connecting, via its conduction nodes , node 304 at node s. In this example, the MPOFF and MPON transistors are respectively a P-channel MOS transistor and an N-channel MOS transistor. The source and the drain of the MPOFF transistor are respectively connected to the node p and to the node s, and the source and the drain of the MNON transistor are respectively connected to node 304 and to node s. The gate of the transistor MNON is connected to the node e3 of application of the control signal SWON1, and the gate of the transistor MPOFF is connected to the node e2 of application of the control signal SWOFF1 via an inverter 607.
    FIG. 7 is an electrical diagram of another exemplary embodiment of a linear voltage regulation circuit LDO1 of the circuit of FIG. 3. As in FIG. 6, we have represented, in addition to the circuit LDO1, the power transistor SW1, as well as
    B15068 - DD16944ST nodes 101 (VDD1), 102 (VCORE) and 304 (VSS) of the voltage selection circuit.
    The circuit LDO1 of FIG. 7 includes a bias circuit (BIAS), a high power node p + is connected to the power node p of the LDO1 circuit and a low power node p- of which is connected to node 304 ( VSS) corresponding to the mass of the circuit. The BIAS bias circuit includes a node if providing a BIASN bias voltage. The LDO1 circuit further comprises a MOS transistor 701 connecting, via its conduction nodes, the supply node p of the LDO1 circuit to an internal node ol, and a MOS transistor 703 connecting, via its conduction nodes, the output node if from the BIAS bias circuit at node 304. In this example, transistor 701 is a P-channel MOS transistor whose source is connected to node p and whose drain is connected to node ol, and transistor 703 is an MOS transistor N-channel whose source is connected to node 304 and whose drain is connected to node if. The gate of transistor 701 is connected to node e4 of application of the activation control signal EN_LDO1 of circuit LDO1, and the gate of transistor 703 is connected to the same node e4 but via an inverter 705, so that transistors 701 and 703 are controlled simultaneously in the open state or simultaneously in the closed state, depending on the state of the signal EN_LDO1. The circuit LDO1 of FIG. 7 further comprises a MOS transistor MPL1 connecting, via its conduction nodes, the supply node p of the circuit LDO1 to its output node s, that is to say to the gate of the transistor SW1. In this example, the transistor MPL1 is a P-channel MOS transistor whose source is connected to the node p and whose drain is connected to the node s. The gate of the transistor MPL1 is connected to the node ol. The circuit LDO1 further comprises a MOS transistor MND1 connecting, via its conduction nodes, the output node s of the circuit LDO1 to an intermediate node o2, and a MOS transistor MNBIAS connecting, via its conduction nodes, the node o2 to the node 304. In this example, the MND1 transistors
    B15068 - DD16944ST and MNBIAS are N-channel MOS transistors. The drain and source of the MND1 transistor are connected to node s and node o2, respectively, and the drain and source of transistor MNBIAS are connected, respectively, to node o2 and node 304. The gate of the transistor MND1 is connected to the node e5 for applying the reference voltage VCTRL, and the gate of the transistor MNBIAS is connected to the output node if of the circuit BIAS. The circuit LDO1 of FIG. 7 further comprises a MOS transistor MPL2 connecting, via its conduction nodes, the supply node p of the circuit LDO1 to the node ol, and a MOS transistor MND2 connecting, via its conduction nodes, the node ol at node o2. In this example, the transistors MPL2 and MND2 are respectively a P-channel MOS transistor and an N-channel MOS transistor. The drain and the source of the MPL2 transistor are connected respectively to the node ol and to the node p, and the drain and the source of the transistor MND2 are connected respectively to the node ol and to the node o2. The gate of the transistor MPL2 is connected to the node ol, and the gate of the transistor MND2 is connected to the input node el of the circuit LDO1, that is to say to the node 102 for supplying the voltage VCORE. The circuit LDO1 of FIG. 7 further comprises a MOS transistor MPOFF connecting, via its conduction nodes, the supply node p of the circuit LDO1 to its output node s, and a MOS transistor MPON connecting, via its conduction nodes , node 304 at node s. In this example, the MPOFF and MPON transistors are respectively a P-channel MOS transistor and an N-channel MOS transistor. The source and the drain of the MPOFF transistor are respectively connected to the node p and to the node s, and the source and the drain of the MNON transistor are respectively connected to node 304 and to node s. The gate of the transistor MNON is connected to the node e3 of application of the control signal SWON1, and the gate of the transistor MPOFF is connected to the node e2 of application of the control signal SWOFF1 via an inverter 707. The circuit of regulation LDO1 of FIG. 7 further comprises a MOS transistor MNBIAS2 connecting, via its conduction nodes, the node el to the node 304. In this example,
    B15068 - DD16944ST the MNBIAS2 transistor is an N-channel MOS transistor whose source and drain are connected respectively to node 304 and to node el. The gate of the transistor MNBIAS2 is connected to the output node if of the bias circuit BIAS. The circuit LDO1 of FIG. 7 further comprises a capacitor CM, a first electrode of which is connected to the node s and the second electrode of which is connected to the node el.
    Particular embodiments have been described. Various variants and modifications will appear to those skilled in the art. In particular, the circuit of FIG. 3 can be simplified if it is known in advance which of the input supply voltages VDD1 and VDD2 is the highest. For example, if it is known in advance that the voltage VDD1 is greater than the voltage VDD2, the linear regulation circuit LDO2 can be omitted, the transistor SW2 then being controlled only in the open state or at closed state. In addition, the transistor SW1_REP for measuring the current flowing in the transistor SW1 can be omitted. In addition, the switches Kl, K2, K3, K4 can be eliminated, the input nodes e- of the ICMP comparator and e- of the VCMP comparator then being connected directly respectively to the node 308 for supplying the current IREP2 and to the node 103 d application of the voltage VDD2. In addition, the nodes 303 and 101 can be confused.
    In addition, in the circuit described in connection with FIG. 3, the circuit formed by the transistors SW1_REP and SW2_REP and by the current comparator ICMP can be replaced by any other circuit adapted to detect an inversion of the current flowing in the transistor SW2 or in transistor SW1.
    Furthermore, as an alternative to using the delay circuit DEL to detect the end of the uplink transitions, provision may be made to make a comparison of the voltage VCORE supplied by the node 102 to the highest of the supply voltages VDD1 and VDD2, for example using the VCMP voltage comparator.
    B15068 - DD16944ST
    In addition, the leakage limiting transistors SWPG1, SWPG2, SWPGMAX can be omitted. In this case, the sources of the transistors SW1, respectively SW2, can be connected directly to the nodes 101, respectively 103, and the nodes 305 and 303 can be merged.
    B15068 - DD16944ST
    权利要求:
    Claims (12)
    [1" id="c-fr-0001]
    1. Supply voltage selection circuit, comprising:
    first (101) and second (103) nodes adapted to receive respectively first (VDD1) and second (VDD2) input supply voltages;
    a third node (102) adapted to supply an output supply voltage (VCORE);
    a first power MOS transistor (SW1) connecting the first node (101) to the third node (102);
    a second power MOS transistor (SW2) connecting the second node (103) to the third node (102); and a control circuit (301) adapted, in a first configuration, to maintain the first (SW1) and second (SW2) transistors respectively closed and open, and, in a second configuration, to maintain the first (SW1) and second ( SW2) transistors respectively open and closed, the control circuit (301) comprising a feedback loop from the third node (102) to the gate of the first transistor (SW1), and being adapted, during a transition phase of the first in the second configuration or from the second to the first configuration, to control the first transistor (SW1) in linear mode to apply a DC voltage ramp to the third node (102).
    [2" id="c-fr-0002]
    2. Selection circuit according to claim 1, in which the control circuit (301) comprises:
    a voltage ramp generator (RMP); and a first linear regulation circuit (LDO1) of which a first input node (el) is connected to the third node (102), of which a second input node (e5) is connected to an output node (s) of the ramp generator (RMP), and one output node (s) of which is connected to the gate of the first transistor (SW1).
    [3" id="c-fr-0003]
    3. Selection circuit according to claim 2, in which the first linear regulation circuit (LDO1) is adapted.
    B15068 - DD16944ST to adjust a control signal applied, via its output node (s), to the gate of the first transistor (SW1), so as to slave the output voltage (VCORE) to a reference voltage applied to its second entry node (e5).
    [4" id="c-fr-0004]
    4. Selection circuit according to claim 2 or 3, further comprising a second linear regulation circuit (LDO2) of which a first input node (el) is connected to the third node (102), including a second input node (e5) is connected to an output node (s) of the ramp generator (RMP), and an output node (s) of which is connected to the gate of the second transistor (SW2).
    [5" id="c-fr-0005]
    5. Selection circuit according to any one of claims 1 to 4, further comprising a circuit (SW2_REP, ICMP) for detecting an inversion of the current flowing in the second transistor (SW2).
    [6" id="c-fr-0006]
    6. Selection circuit according to claim 5, in which the detection circuit comprises a measurement transistor (SW2_REP) arranged to be crossed by a measurement current (IREP2) proportional to the current passing through the second transistor (SW2), and a comparator current (ICMP) adapted to compare said measurement current (IREP2) a threshold (IREVLIM).
    [7" id="c-fr-0007]
    7. Selection circuit according to any one of claims 1 to 6, further comprising a circuit (VCMP) for comparing the output voltage (VCORE) with a threshold.
    [8" id="c-fr-0008]
    8. Selection circuit according to any one of claims 1 to 7, further comprising a circuit (LED) for generating a predetermined delay.
    [9" id="c-fr-0009]
    9. Selection circuit according to any one of claims 1 to 8, in which the first power MOS transistor (SW1) is connected to the first node (101) via a first additional MOS transistor (SWPG1) having leakage currents in the blocked state lower than that of the first power MOS transistor (SW1), and in which the second power MOS transistor (SW2) is connected to the second node (103) via a second
    B15068 - DD16944ST additional MOS transistor (SWPG2) with leakage currents in the blocked state lower than that of the second power MOS transistor (SW2).
    [10" id="c-fr-0010]
    10. Selection circuit according to claim 9, in which the control circuit (301) is adapted, in a third configuration, to maintain the first (SW1) and second (SW2) power MOS transistors and the first (SWPG1) and second (SWPG2) additional MOS transistors in the open state.
    [11" id="c-fr-0011]
    11. Selection circuit according to any one of claims 1 to 10, in which the first input supply voltage (VDD1) is greater than the second input supply voltage (VDD2), the control circuit (301) being adapted, during a downward transition phase between the first and second configurations, to:
    controlling the first transistor (SW1) in linear mode to apply a decreasing DC voltage ramp to the third node (102);
    detecting a passage of the output voltage (VCORE) at a level substantially equal to that of the second input supply voltage (VDD2); and when the output voltage (VCORE) reaches a level substantially equal to that of the second input supply voltage (VDD2), close the second power MOS transistor (SW2) and open the first power MOS transistor (SW1 ).
    [12" id="c-fr-0012]
    12. Selection circuit according to any one of claims 1 to 11, in which the first input supply voltage (VDD1) is greater than the second input supply voltage (VDD2), the control circuit (301) being adapted, during an upward transition phase between the first and second configurations, to:
    controlling the first transistor (SW1) in linear mode to apply a ramp of increasing direct voltage to the third node (102);
    detecting an inversion of the current flowing in the second transistor (SW2);
    B15068 - DD16944ST when the current flowing in the second transistor (SW2) reverses, open the second transistor (SW2); and after a predetermined delay, closing the first power MOS transistor (SW1).
    B15068 DD16944ST
    1/4
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    同族专利:
    公开号 | 公开日
    US20180012635A1|2018-01-11|
    US10127953B2|2018-11-13|
    EP3267583B1|2021-03-24|
    FR3053857B1|2020-03-27|
    EP3267583A1|2018-01-10|
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    法律状态:
    2017-07-31| PLFP| Fee payment|Year of fee payment: 2 |
    2018-01-12| PLSC| Search report ready|Effective date: 20180112 |
    2018-07-27| PLFP| Fee payment|Year of fee payment: 3 |
    2019-07-31| PLFP| Fee payment|Year of fee payment: 4 |
    2020-07-31| PLFP| Fee payment|Year of fee payment: 5 |
    2021-07-29| PLFP| Fee payment|Year of fee payment: 6 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1656566A|FR3053857B1|2016-07-07|2016-07-07|CIRCUIT FOR SELECTING A SUPPLY VOLTAGE WITH CONTROLLED TRANSITION|
    FR1656566|2016-07-07|FR1656566A| FR3053857B1|2016-07-07|2016-07-07|CIRCUIT FOR SELECTING A SUPPLY VOLTAGE WITH CONTROLLED TRANSITION|
    EP17176497.0A| EP3267583B1|2016-07-07|2017-06-16|Circuit for selecting a supply voltage with controlled transition|
    US15/628,074| US10127953B2|2016-07-07|2017-06-20|Circuit for selecting a power supply voltage having a controlled transition|
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